The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 21, 2017

Filed:

Apr. 27, 2015
Applicants:

Wei-sheng Lei, San Jose, CA (US);

Brad Eaton, Menlo Park, CA (US);

Jungrae Park, Santa Clara, CA (US);

Ajay Kumar, Cupertino, CA (US);

James S. Papanu, San Rafael, CA (US);

Prabhat Kumar, Fremont, CA (US);

Inventors:

Wei-Sheng Lei, San Jose, CA (US);

Brad Eaton, Menlo Park, CA (US);

Jungrae Park, Santa Clara, CA (US);

Ajay Kumar, Cupertino, CA (US);

James S. Papanu, San Rafael, CA (US);

Prabhat Kumar, Fremont, CA (US);

Assignee:

Applied Materials, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/301 (2006.01); H01L 21/46 (2006.01); H01L 21/78 (2006.01); H01L 21/447 (2006.01); H01L 21/48 (2006.01); H01L 21/50 (2006.01); H01L 21/308 (2006.01); H01L 21/3065 (2006.01); H01L 21/268 (2006.01); H01L 21/67 (2006.01); H01L 21/683 (2006.01);
U.S. Cl.
CPC ...
H01L 21/78 (2013.01); H01L 21/268 (2013.01); H01L 21/3065 (2013.01); H01L 21/3086 (2013.01); H01L 21/67069 (2013.01); H01L 21/6836 (2013.01);
Abstract

Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits on a front side of the semiconductor wafer includes adhering a back side the semiconductor wafer on the dicing tape of a substrate carrier. Subsequent to adhering the semiconductor wafer on a dicing tape, the dicing tape is treated with a UV-cure process. Subsequent to treating the dicing tape with the UV-cure process, a dicing mask is formed on the front side of the semiconductor wafer, the dicing mask covering and protecting the integrated circuits. The dicing mask is patterned with a laser scribing process to provide gaps in the dicing mask, the gaps exposing regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is plasma etched through the gaps in the dicing mask layer to singulate the integrated circuits.


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