The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 07, 2017

Filed:

Jun. 28, 2013
Applicants:

Cheong Min Hong, Austin, TX (US);

Sung-taeg Kang, Austin, TX (US);

Inventors:

Cheong Min Hong, Austin, TX (US);

Sung-Taeg Kang, Austin, TX (US);

Assignee:

NXP USA, INC., Austin, TX (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/788 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 21/28 (2006.01); H01L 27/105 (2006.01); H01L 27/115 (2006.01);
U.S. Cl.
CPC ...
H01L 29/42332 (2013.01); H01L 21/28282 (2013.01); H01L 27/105 (2013.01); H01L 27/11536 (2013.01); H01L 29/42328 (2013.01); H01L 29/66825 (2013.01); H01L 29/66833 (2013.01); H01L 29/7881 (2013.01);
Abstract

A method of forming a split gate memory cell structure using a substrate includes forming a gate stack comprising a select gate and a dielectric portion overlying the select gate. A charge storage layer is formed over the substrate including over the gate stack. A first sidewall spacer of conductive material is formed along a first sidewall of the gate stack extending past a top of the select gate. A second sidewall spacer of dielectric material is formed along the first sidewall on the first sidewall spacer. A portion of the first sidewall spacer is silicided using the second sidewall spacer as a mask whereby silicide does not extend to the charge storage layer.


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