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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9583352 B1

PDFFull Text
Date of Patent:
Feb. 28, 2017

Filed:

Aug. 18, 2015

Method of etching and cleaning wafers

Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Wen-Chang Tsai, Hsinchu, TW;

Shao-Yen Ku, Jhubei, TW;

Hsieh-Ching Wei, Hsinchu, TW;

Yuan Chih Chiang, Hsinchu, TW;

Jui-Chuan Chang, Hsinchu, TW;

Yung-Li Tsai, Houlong Town, TW;

Assignee:

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., , TW;

Attorney:

Hauptman Ham, LLP

Primary Examiner:

Victor A Mandala

Assistant Examiner:

Regan J Rundio

Int. Cl.
CPC ...
H01L 21/306 (2006.01); H01L 21/66 (2006.01); H01L 21/677 (2006.01); H01L 21/02 (2006.01); H01L 21/673 (2006.01); H01L 21/67 (2006.01); G05B 19/418 (2006.01);
U.S. Cl.
CPC ...
H01L 21/30604 (2013.01); G05B 19/4187 (2013.01); H01L 21/02076 (2013.01); H01L 21/67017 (2013.01); H01L 21/67023 (2013.01); H01L 21/67028 (2013.01); H01L 21/67063 (2013.01); H01L 21/6773 (2013.01); H01L 21/67242 (2013.01); H01L 21/67253 (2013.01); H01L 21/67386 (2013.01); H01L 21/67389 (2013.01); H01L 21/67393 (2013.01); H01L 21/67766 (2013.01); H01L 21/67769 (2013.01); H01L 21/67772 (2013.01); H01L 21/67775 (2013.01); H01L 21/67781 (2013.01); H01L 22/20 (2013.01); H01L 21/02019 (2013.01); H01L 21/67069 (2013.01); H01L 21/67075 (2013.01); H01L 21/67265 (2013.01); Y02P 90/20 (2015.11); Y02P 90/205 (2015.11); Y10S 414/135 (2013.01); Y10S 414/14 (2013.01);
Abstract

A method of operating a wafer processing system includes etching a batch of wafers. The method also includes transferring at least a portion of the batch of wafers to a first front opening universal pod (FOUP). The method further includes purging an interior of the first FOUP with an inert gas. The method additionally includes transporting the first FOUP from a first loading port to a second loading port. The method also includes monitoring an elapsed time from the purging. The method further includes performing a second purging of the interior of the first FOUP if the elapsed time exceeds a threshold time. The method additionally includes cleaning the batch of wafers.

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