The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 28, 2017

Filed:

Apr. 06, 2016
Applicants:

Commissariat a L'energie Atomique ET Aux Energies Alternatives, Paris, FR;

Cnrs Centre National DE LA Recherche Scientifique, Paris, FR;

Applied Materials, Inc., Santa Clara, CA (US);

Inventors:

Nicolas Posseme, Grenoble, FR;

Thibaut David, Goncelin, FR;

Olivier Joubert, Meylan, FR;

Thorsten Lill, Santa Clara, CA (US);

Srinivas Nemani, Santa Clara, CA (US);

Laurent Vallier, Meylan, FR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/302 (2006.01); H01L 21/02 (2006.01); H01L 21/306 (2006.01); H01L 21/265 (2006.01); H01L 21/3065 (2006.01);
U.S. Cl.
CPC ...
H01L 21/0234 (2013.01); H01L 21/02532 (2013.01); H01L 21/26506 (2013.01); H01L 21/3065 (2013.01); H01L 21/30604 (2013.01);
Abstract

A method is provided for forming spacers for a gate of a field effect transistor, the gate being situated above a layer of semiconductor material, including forming a layer of nitride covering the gate; modifying the layer by plasma implantation of light ions, having an atomic number equal or less than 10, in the layer in order to form a modified layer of nitride, the modifying being performed so as not to modify the layer of nitride over its entire thickness at flanks of the gate; and removing the modified layer of nitride by a selective wet or dry etching, of the modified layer relative to said layer of semiconductor material and relative to the non-modified layer at the flanks of the gate, without etching the layer of semiconductor material, wherein an entire length of the non-modified layer at the flanks remains after the selective wet or dry etching.


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