The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 21, 2017
Filed:
Apr. 02, 2014
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;
Trinh Hai Dang, Hsinchu, TW;
Hsing-Lien Lin, Hsin-Chu, TW;
Kai-Wen Cheng, Taichung, TW;
Cheng-Yuan Tsai, Chu-Pei, TW;
Chia-Shiung Tsai, Hsin-Chu, TW;
Ru-Liang Lee, Hsinchu, TW;
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;
Abstract
The present disclosure relates to a method of forming a resistive random access memory (RRAM) cell having a reduced leakage current, and an associated apparatus. In some embodiments, the method is performed by forming a bottom electrode over a lower metal interconnect layer using an atomic layer deposition (ALD) process to form at least a top portion of the bottom electrode. A dielectric data storage layer is formed onto the top portion of the bottom electrode in-situ with forming the top portion of the bottom electrode. A top electrode is formed over the dielectric data storage layer, and an upper metal interconnect layer is formed over the top electrode. By forming the top portion of the bottom electrode using an ALD process that is in-situ with the formation of the overlying dielectric data storage layer, leakage current, leakage current distribution and device yield of the RRAM cell are improved.