The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 14, 2017
Filed:
Oct. 01, 2014
Applicant:
Netspeed Systems, San Jose, CA (US);
Inventors:
Sailesh Kumar, San Jose, CA (US);
Sandip Das, San Francisco, CA (US);
Poonacha Kongetira, Saratoga, CA (US);
Assignee:
NetSpeed Systems, San Jose, CA (US);
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); H04L 12/24 (2006.01); H04L 12/751 (2013.01); H04L 12/933 (2013.01); H04L 12/803 (2013.01);
U.S. Cl.
CPC ...
H04L 41/0816 (2013.01); H04L 41/0833 (2013.01); H04L 45/08 (2013.01); H04L 47/125 (2013.01); H04L 49/109 (2013.01);
Abstract
An aspect of the present disclosure provides a hardware element in a Network on Chip (NoC), wherein the hardware element includes a clock gating circuit configures one or more neighboring hardware elements to activate before receiving new incoming data and to sleep after a defined number of cycles, wherein the defined number of cycles can be counted from a cycle having non-receipt of incoming data and/or having a clearance of all data within an input queue of a source hardware element.