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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9570581 B1

PDFFull Text
Date of Patent:
Feb. 14, 2017

Filed:

Apr. 05, 2016

Method of forming a self-aligned stack gate structure for use in a non-volatile memory array

Applicant:

Silicon Storage Technology, Inc., San Jose, CA (US);

Inventors:

Willem-Jan Toren, St. Maximin, FR;

Xian Liu, Sunnyvale, CA (US);

Gerhard Metzger-Brueckl, Geisenfeld, DE;

Nhan Do, Saratoga, CA (US);

Stephan Wege, Bannewitz-Cunnersdorf, DE;

Nadia Miridi, Auroil, FR;

Chieng-Sheng Su, Saratoga, CA (US);

Cecile Bernardi, Bouc Bel Air, FR;

Liz Cuevas, Los Gatos, CA (US);

Florence Guyot, Venelles, FR;

Yueh-Hsin Chen, Pleasanton, CA (US);

Henry Om'mani, Santa Clara, CA (US);

Mandana Tadayoni, Cupertino, CA (US);

Assignee:

Silicon Storage Technology, Inc., San Jose, CA (US);

Attorney:

DLA Piper LLP (US)

Primary Examiner:

Mark Tornow

Int. Cl.
CPC ...
H01L 29/788 (2006.01); H01L 29/66 (2006.01); H01L 21/28 (2006.01); H01L 27/115 (2006.01); H01L 21/762 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66545 (2013.01); H01L 21/28273 (2013.01); H01L 21/28282 (2013.01); H01L 21/76283 (2013.01); H01L 27/11521 (2013.01); H01L 27/11568 (2013.01);
Abstract

A stack gate structure for a non-volatile memory array has a semiconductor substrate having a plurality of substantially parallel spaced apart active regions, with each active region having an axis in a first direction. A first insulating material is between each stack gate structure in the second direction perpendicular to the first direction. Each stack gate structure has a second insulating material over the active region, a charge holding gate over the second insulating material, a third insulating material over the charge holding gate, and a first portion of a control gate over the third insulating material. A second portion of the control gate is over the first portion of the control gate and over the first insulating material adjacent thereto and extending in the second direction. A fourth insulating material is over the second portion of the control gate.

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