The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 07, 2017

Filed:

Apr. 22, 2014
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Mong-Song Liang, Taipei, TW;

Tze-Liang Lee, Hsin-Chu, TW;

Kuo-Tai Huang, Hsin-Chu, TW;

Chao-Cheng Chen, Hsin-Chu, TW;

Hao-Ming Lien, Hsin-Chu, TW;

Chih-Tang Peng, Zhubei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/10 (2006.01); H01L 21/762 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 29/1054 (2013.01); H01L 21/76224 (2013.01); H01L 29/7843 (2013.01); H01L 29/7846 (2013.01); H01L 29/7833 (2013.01);
Abstract

A method of forming an isolation trench having localized stressors is provided. In accordance with embodiments of the present invention, a trench is formed in a substrate and partially filled with a dielectric material. In an embodiment, the trench is filled with a dielectric layer and a planarization step is performed to planarize the surface with the surface of the substrate. The dielectric material is then recessed below the surface of the substrate. In the recessed portion of the trench, the dielectric material may remain along the sidewalls or the dielectric material may be removed along the sidewalls. A stress film, either tensile or compressive, may then be formed over the dielectric material within the recessed portion. The stress film may also extend over a transistor or other semiconductor structure.


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