The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 07, 2017

Filed:

Jan. 28, 2016
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Reinhard Mahnkopf, Oberhaching, DE;

Wolfgang Molzer, Ottobrunn, DE;

Bernd Memmler, Riemerling, DE;

Edmund Goetz, Dachau, DE;

Hans-Joachim Barth, Munich, DE;

Sven Albers, Regensburg, DE;

Thorsten Meyer, Regensburg, DE;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/44 (2006.01); H01L 23/538 (2006.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 23/00 (2006.01); H01L 25/07 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2006.01); H01L 23/31 (2006.01); H01L 21/56 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5389 (2013.01); H01L 21/563 (2013.01); H01L 21/76898 (2013.01); H01L 23/5226 (2013.01); H01L 23/5384 (2013.01); H01L 23/562 (2013.01); H01L 24/03 (2013.01); H01L 24/81 (2013.01); H01L 25/0657 (2013.01); H01L 25/074 (2013.01); H01L 25/50 (2013.01); H01L 21/56 (2013.01); H01L 23/3121 (2013.01); H01L 2224/08146 (2013.01); H01L 2224/16148 (2013.01); H01L 2224/73204 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06544 (2013.01); H01L 2225/06548 (2013.01); H01L 2225/06568 (2013.01);
Abstract

Embodiments of the present description include stacked microelectronic dice embedded in a microelectronic substrate and methods of fabricating the same. In one embodiment, at least one first microelectronic die is attached to a second microelectronic die, wherein an underfill material is provided between the second microelectronic die and the at least one first microelectronic die. The microelectronic substrate is then formed by laminating the first microelectronic die and the second microelectronic die in a substrate material.


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