The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 17, 2017

Filed:

Feb. 09, 2012
Applicants:

Stephan Kronholz, Dresden, DE;

Nadja Zakowsky, Radeburg, DE;

Yew Tuck Chow, Dresden, DE;

Inventors:

Stephan Kronholz, Dresden, DE;

Nadja Zakowsky, Radeburg, DE;

Yew Tuck Chow, Dresden, DE;

Assignee:

GLOBALFOUNDRIES, INC., Grand Cayman, KY;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/20 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/10 (2006.01); H01L 21/02 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66651 (2013.01); H01L 21/0245 (2013.01); H01L 29/1054 (2013.01); H01L 29/7833 (2013.01); H01L 21/02035 (2013.01); H01L 21/0243 (2013.01); H01L 21/02532 (2013.01); H01L 21/02617 (2013.01);
Abstract

A method for forming field effect transistors (FETs) in a multiple wafers per batch epi-reactor includes, providing substrates having therein at least one semiconductor (SC) region with a substantially flat outer surface, modifying such substantially flat outer surface to form a convex-outward curved surface, forming an epitaxial semiconductor layer on the curved surface, and incorporating the epitaxial layer in a field effect transistor formed on the substrate. Where the SC region is of silicon, the epitaxial layer can include silicon-germanium. In a preferred embodiment, the epi-layer forms part of the FET channel. Because of the convex-outward curved surface, the epi-layer grown thereon has much more uniform thickness even when formed in a high volume reactor holding as many as 100 or more substrates per batch. FETs with much more uniform properties are obtained, thereby greatly increasing the manufacturing yield and reducing the cost.


Find Patent Forward Citations

Loading…