The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 10, 2017

Filed:

Aug. 21, 2015
Applicant:

Sandisk Technologies Inc., Plano, TX (US);

Inventors:

Zhenyu Lu, Milpitas, CA (US);

Daxin Mao, Cupertino, CA (US);

Koji Miyata, Yokkaichi, JP;

Junichi Ariyoshi, Yokkaichi, JP;

Johann Alsmeier, San Jose, CA (US);

George Matamis, Danville, CA (US);

Wenguang Shi, Milpitas, CA (US);

Jiyin Xu, Yokkaichi, JP;

Xiaolong Hu, Yokkaichi, JP;

Assignee:

SANDISK TECHNOLOGIES LLC, Plano, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/115 (2006.01); H01L 21/28 (2006.01); H01L 29/423 (2006.01); H01L 29/792 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); H01L 21/28282 (2013.01); H01L 29/4234 (2013.01); H01L 29/66833 (2013.01); H01L 29/7926 (2013.01);
Abstract

An alternating stack of insulator layers and spacer material layers is formed over a substrate. Stepped surfaces are formed in a contact region in which contact via structures are to be subsequently formed. An epitaxial semiconductor pedestal can be formed by a single epitaxial deposition process that is performed after formation of the stepped surfaces and prior to formation of memory openings, or a combination of a first epitaxial deposition process performed prior to formation of memory openings and a second epitaxial deposition process performed after formation of the memory openings. The epitaxial semiconductor pedestal can have a top surface that is located above a topmost surface of the alternating stack. The spacer material layers are formed as, or can be replaced with, electrically conductive layers. Backside contact via structures can be subsequently formed.


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