The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 10, 2017

Filed:

Oct. 01, 2008
Applicants:

Georg Pietsch, Burghausen, DE;

Michael Kerstan, Burghausen, DE;

Heiko Aus Dem Spring, Weilburg, DE;

Inventors:

Georg Pietsch, Burghausen, DE;

Michael Kerstan, Burghausen, DE;

Heiko aus dem Spring, Weilburg, DE;

Assignees:

Siltronic AG, Munich, DE;

Peter Wolters GmbH, Rendsburg, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
B24B 37/08 (2012.01); B24B 37/28 (2012.01); B24B 37/32 (2012.01); B24B 37/04 (2012.01);
U.S. Cl.
CPC ...
B24B 37/28 (2013.01); B24B 37/042 (2013.01); B24B 37/08 (2013.01); B24B 37/32 (2013.01); Y10T 29/49 (2015.01);
Abstract

Carriers suitable for receiving one or more semiconductor wafers for the machining thereof in lapping, grinding or polishing machines, comprise a core of a first material which has a high stiffness, the core being completely or partly coated with a second material, and also at least one cutout for receiving a semiconductor wafer, wherein the second material is a thermoset polyurethane elastomer having a Shore A hardness of 20-90. The carriers are preferably coated with the second material after chemical surface activation and application of adhesion promoter, and may be used for simultaneous double-side material-removing machining of a plurality of semiconductor wafers.


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