The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 03, 2017
Filed:
May. 24, 2011
Applicants:
Chii-ming Wu, Taipei, TW;
Chien-chang Su, Kaohsiung, TW;
Hsien-hsin Lin, Hsin-Chu, TW;
Yi-fang Pai, Hsin-Chu, TW;
Inventors:
Chii-Ming Wu, Taipei, TW;
Chien-Chang Su, Kaohsiung, TW;
Hsien-Hsin Lin, Hsin-Chu, TW;
Yi-Fang Pai, Hsin-Chu, TW;
Assignee:
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 21/336 (2006.01); H01L 21/225 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7834 (2013.01); H01L 21/2257 (2013.01); H01L 29/6659 (2013.01); H01L 29/66628 (2013.01); H01L 29/66636 (2013.01);
Abstract
A system and method for forming semiconductor structures is disclosed. An embodiment comprises forming a high diffusibility layer adjacent to a gate stack and forming a low diffusibility layer adjacent to the high diffusibility layer. After these two layers are formed, an anneal is performed to diffuse dopants from the high diffusibility layer underneath the gate stack to help form a channel region.