The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 29, 2016

Filed:

Dec. 30, 2011
Applicants:

Mauro J. Kobrinsky, Portland, OR (US);

Henning Braunisch, Chandler, AZ (US);

Shawna M. Liff, Gilbert, AZ (US);

Peter L. Chang, Portland, OR (US);

Bruce A. Block, Portland, OR (US);

Johanna M. Swan, Scottsdale, AZ (US);

Inventors:

Mauro J. Kobrinsky, Portland, OR (US);

Henning Braunisch, Chandler, AZ (US);

Shawna M. Liff, Gilbert, AZ (US);

Peter L. Chang, Portland, OR (US);

Bruce A. Block, Portland, OR (US);

Johanna M. Swan, Scottsdale, AZ (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04B 10/25 (2013.01); G02B 6/12 (2006.01); G02B 6/42 (2006.01); G02B 6/30 (2006.01);
U.S. Cl.
CPC ...
G02B 6/12 (2013.01); G02B 6/30 (2013.01); G02B 6/428 (2013.01); G02B 6/4214 (2013.01); H04B 10/25 (2013.01); G02B 2006/12061 (2013.01);
Abstract

Photonic components are placed on the processor package to bring the optical signal close to the processor die. The processor package includes a substrate to which the processor die is coupled, and which allows the processor die to connect to a printed circuit board. The processor package also includes transceiver logic, electrical-optical conversion circuits, and an optical coupler. The electrical-optical conversion circuits can include laser(s), modulator(s), and photodetector(s) to transmit and receive and optical signal. The coupler interfaces to a fiber that extends off the processor package. Multiple fibers can be brought to the processor package allowing for a scalable high-speed, high-bandwidth interconnection to the processor.


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