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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9497862 B1

PDFFull Text
Date of Patent:
Nov. 15, 2016

Filed:

Jan. 20, 2012

Packaging structure

Applicants:

Lei Shi, Nantong, CN;

Yujuan Tao, Nantong, CN;

Guohua Gao, Nantong, CN;

Guoji Yang, Nantong, CN;

Honglei LI, Nantong, CN;

Haijun Shen, Nantong, CN;

Inventors:

Lei Shi, Nantong, CN;

Yujuan Tao, Nantong, CN;

Guohua Gao, Nantong, CN;

Guoji Yang, Nantong, CN;

Honglei Li, Nantong, CN;

Haijun Shen, Nantong, CN;

Assignee:

Nantong Fujitsu Microelectronics Co., Ltd., Nantong, CN;

Attorney:

RatnerPrestia

Primary Examiner:

Julio J Maldonado

Assistant Examiner:

Cory Eskridge

Int. Cl.
CPC ...
H01L 23/34 (2006.01); H05K 1/18 (2006.01); H01L 21/56 (2006.01); H01L 23/31 (2006.01); H01L 23/498 (2006.01); H01L 23/538 (2006.01); H01L 25/16 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H05K 1/181 (2013.01); H01L 21/561 (2013.01); H01L 21/568 (2013.01); H01L 23/3128 (2013.01); H01L 23/49816 (2013.01); H01L 23/5389 (2013.01); H01L 24/19 (2013.01); H01L 24/96 (2013.01); H01L 25/165 (2013.01); H01L 24/24 (2013.01); H01L 2224/12105 (2013.01); H01L 2224/24195 (2013.01); H01L 2224/821 (2013.01); H01L 2924/12042 (2013.01); H01L 2924/1815 (2013.01);
Abstract

The present invention relates a packaging structure including: a carrier board and a cementing layer on the surface of the carrier board; chips and passive devices having functional side thereof attached to the cementing layer; and a sealing material layer for packaging and curing, the sealing material being formed on the carrier board on the side attached to the chips and the passive devices. The present invention integrates chips and passive devices and then packages the chips and the passive devices together, and is therefore a packaged product having not single-chip functionality but integrated-system functionality. The present invention is highly integrated, reduces interfering factors such as system-internal electric resistance and inductance, and accommodates growing demand for lighter, thinner, shorter, and smaller semiconductor packaging.

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Shi, Lei. (2016). Packaging structure (U.S. Patent No. 9497862). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9497862

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