The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 15, 2016

Filed:

Jan. 30, 2013
Applicant:

Ibiden Co., Ltd., Ogaki-shi, JP;

Inventors:

Takashi Kariya, Ogaki, JP;

Toshiki Furutani, Ogaki, JP;

Takeshi Furusawa, Ogaki, JP;

Assignee:

IBIDEN CO., LTD., Ogaki-shi, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H05K 1/02 (2006.01); H05K 3/46 (2006.01); H01L 21/48 (2006.01); H01L 23/498 (2006.01);
U.S. Cl.
CPC ...
H05K 1/02 (2013.01); H01L 21/486 (2013.01); H01L 23/49827 (2013.01); H01L 23/49894 (2013.01); H05K 3/4644 (2013.01); H01L 23/49816 (2013.01); H01L 23/49822 (2013.01); H01L 2924/0002 (2013.01); H05K 1/0271 (2013.01); H05K 2201/029 (2013.01); H05K 2201/09136 (2013.01);
Abstract

A printed wiring board includes a core substrate, first and second buildup structures on surfaces of the core, respectively, and first and second solder-resist layers on the first and second structures, respectively. The core includes insulative substrate, conductive layers on surfaces of the substrate and through-hole conductor connecting the conductive layers, the first structure includes interlayer insulation layer and conductive layer in the first structure, the second structure includes interlayer insulation layer and conductive layer in the second structure, a thickness between the outer surfaces of the first and second solder-resist layers is set in range of from 150 μm or greater and less than 380 μm, and at least one of the core, first and second structures, and first and second solder-resist layers includes reinforcing material in amount such that the board includes the material in amount in range of from 20 to 35 vol. %.


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