Methods for layout verification for polysilicon cell edge structures in finfet standard cells using filters

Abstract

Methods for verifying the layout for standard cells using finFET standard cell structures with polysilicon on cell edges. Standard cells are defined using finFET transistors. Polysilicon dummy structures are formed on the edges of the active areas of the standard cells. Where two standard cells abut a single polysilicon dummy structure is formed. In a design flow, a pre-layout netlist schematic for the standard cells is formed that does not include devices corresponding to the polysilicon dummy structures. After an automated place and route process forms a device layout using the standard cells, a post layout netlist schematic is extracted including MOS devices corresponding to the polysilicon dummy structures. A layout versus schematic comparison is then performed, but during the comparison MOS devices corresponding to the polysilicon dummy structures are filtered from the post-layout netlist and are not compared. Additional methods are disclosed.