The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 08, 2016

Filed:

Jun. 19, 2015
Applicant:

Unisantis Electronics Singapore Pte. Ltd., Singapore, SG;

Inventors:

Fujio Masuoka, Tokyo, JP;

Nozomu Harada, Tokyo, JP;

Hiroki Nakamura, Tokyo, JP;

Yisuo Li, Singapore, SG;

Aashit Ramachandra Kamath, Singapore, SG;

Zhixian Chen, Singapore, SG;

Teng Soong Phua, Singapore, SG;

Xinpeng Wang, Singapore, SG;

Patrick Guo-Qiang Lo, Singapore, SG;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/423 (2006.01); H01L 29/49 (2006.01); H01L 27/092 (2006.01); H01L 21/8238 (2006.01); H01L 21/28 (2006.01); H01L 21/285 (2006.01); H01L 21/3213 (2006.01); H01L 21/8234 (2006.01); H01L 27/088 (2006.01); H01L 29/06 (2006.01); H01L 29/10 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7827 (2013.01); H01L 21/28035 (2013.01); H01L 21/28238 (2013.01); H01L 21/28518 (2013.01); H01L 21/32134 (2013.01); H01L 21/32139 (2013.01); H01L 21/823437 (2013.01); H01L 21/823475 (2013.01); H01L 21/823487 (2013.01); H01L 21/823885 (2013.01); H01L 27/088 (2013.01); H01L 27/092 (2013.01); H01L 29/0692 (2013.01); H01L 29/1037 (2013.01); H01L 29/1054 (2013.01); H01L 29/423 (2013.01); H01L 29/42356 (2013.01); H01L 29/49 (2013.01); H01L 29/4916 (2013.01); H01L 29/66666 (2013.01);
Abstract

A semiconductor device production method includes a first step of forming a planar silicon layer on a silicon substrate and forming first and second pillar-shaped silicon layers on the planar silicon layer; a second step of forming a gate insulating film around the first and second pillar-shaped silicon layers, forming a metal film and a polysilicon film around the gate insulating film, controlling a thickness of the polysilicon film to be smaller than a half of a distance between the first and second pillar-shaped silicon layers, depositing a resist, exposing the polysilicon film on side walls of upper portions of the first and second pillar-shaped semiconductor layers, etching-away the exposed polysilicon film, stripping the third resist, and etching-away the metal film; and a third step of forming a resist for forming a gate line and performing anisotropic etching to form a gate line and first and second gate electrodes.


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