The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 01, 2016

Filed:

Nov. 18, 2015
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Peter Javorka, Radeburg, DE;

Stephan Kronholz, Dresden, DE;

Gunda Beernink, Dresden, DE;

Assignee:

GLOBALFOUNDRIES Inc., Grand Cayman, KY;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/10 (2006.01); H01L 29/78 (2006.01); H01L 29/10 (2006.01); H01L 29/165 (2006.01); H01L 29/417 (2006.01); H01L 29/66 (2006.01); H01L 21/8234 (2006.01); H01L 29/04 (2006.01); H01L 29/51 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7848 (2013.01); H01L 21/823412 (2013.01); H01L 21/823418 (2013.01); H01L 21/823425 (2013.01); H01L 29/04 (2013.01); H01L 29/1054 (2013.01); H01L 29/165 (2013.01); H01L 29/41783 (2013.01); H01L 29/6653 (2013.01); H01L 29/6656 (2013.01); H01L 29/6659 (2013.01); H01L 29/7834 (2013.01); H01L 29/517 (2013.01);
Abstract

A semiconductor device includes drain and source regions positioned in an active region of a transistor and a channel region positioned laterally between the drain and source regions that includes a semiconductor base material and a threshold voltage adjusting semiconductor material positioned on the semiconductor base material. A gate electrode structure is positioned on the threshold voltage adjusting semiconductor material, and a strain-inducing semiconductor alloy including a first semiconductor material and a second semiconductor material positioned above the first semiconductor material is embedded in the semiconductor base material of the active region. A crystalline buffer layer of a third semiconductor material surrounds the embedded strain-inducing semiconductor alloy, wherein an upper portion of the crystalline buffer layer laterally confines the channel region including the sidewalls of the threshold voltage adjusting semiconductor material and is positioned between the second semiconductor material and the threshold voltage adjusting semiconductor material.


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