The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 11, 2016

Filed:

Mar. 12, 2014
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Inventors:

Ru-Shang Hsiao, Jhubei, TW;

Ling-Sung Wang, Tainan, TW;

Chih-Mu Huang, Tainan, TW;

Cing-Yao Chan, Keelung, TW;

Chun-Ying Wang, Tainan, TW;

Jen-Pan Wang, Tainan, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H02H 9/00 (2006.01); H01L 29/10 (2006.01); H01L 29/78 (2006.01); H01L 29/165 (2006.01); H01L 29/16 (2006.01); H01L 29/161 (2006.01); H01L 21/02 (2006.01); H01L 21/306 (2006.01); H01L 21/8238 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/1054 (2013.01); H01L 21/02381 (2013.01); H01L 21/02529 (2013.01); H01L 21/02532 (2013.01); H01L 21/30604 (2013.01); H01L 21/823807 (2013.01); H01L 29/161 (2013.01); H01L 29/165 (2013.01); H01L 29/1608 (2013.01); H01L 29/66575 (2013.01); H01L 29/66651 (2013.01); H01L 29/7842 (2013.01); H01L 29/66545 (2013.01);
Abstract

The present disclosure relates to a method of forming a transistor device having a channel region comprising a sandwich film stack with a plurality of different layers that improve device performance, and an associated apparatus. In some embodiments, the method is performed by selectively etching a semiconductor substrate to form a recess along a top surface of the semiconductor substrate. A sandwich film stack having a plurality of nested layers is formed within the recess. At least two of the nested layers include different materials that improve different aspects of the performance of the transistor device. A gate structure is formed over the sandwich film stack. The gate structure controls the flow of charge carriers in a channel region having the sandwich film stack, which is laterally positioned between a source region and a drain region disposed within the semiconductor substrate.


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