The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 11, 2016

Filed:

May. 09, 2014
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Jae Sik Lee, San Diego, CA (US);

Hong Bok We, San Diego, CA (US);

Dong Wook Kim, San Diego, CA (US);

Shiqun Gu, San Diego, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/4763 (2006.01); H01L 23/48 (2006.01); H01L 23/50 (2006.01); H01L 21/56 (2006.01); H01L 21/768 (2006.01); H01L 23/498 (2006.01); H01L 25/10 (2006.01); H01L 25/065 (2006.01);
U.S. Cl.
CPC ...
H01L 23/481 (2013.01); H01L 21/56 (2013.01); H01L 21/76802 (2013.01); H01L 21/76877 (2013.01); H01L 23/49827 (2013.01); H01L 23/50 (2013.01); H01L 25/105 (2013.01); H01L 25/0655 (2013.01); H01L 2224/16225 (2013.01); H01L 2225/1023 (2013.01); H01L 2225/1058 (2013.01); H01L 2924/1533 (2013.01); H01L 2924/15311 (2013.01);
Abstract

Some novel features pertain to an integrated device that includes an encapsulation layer, a via structure traversing the encapsulation layer, and a pad. The via structure includes a via that includes a first side, a second side, and a third side. The via structure also includes a barrier layer surrounding at least the first side and the third side of the via. The pad is directly coupled to the barrier layer of the via structure. In some implementations, the integrated device includes a first dielectric layer coupled to a first surface of the encapsulation layer. In some implementations, the integrated device includes a substrate coupled to a first surface of the encapsulation layer. In some implementations, the integrated device includes a first die coupled to the substrate, where the encapsulation layer encapsulates the first die. In some implementations, the via includes a portion configured to operate as a pad.


Find Patent Forward Citations

Loading…