The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 27, 2016

Filed:

Mar. 25, 2012
Applicants:

Arijit Raychowdhury, Duluth, GA (US);

David Kencke, Beaverton, OR (US);

Brian Doyle, Portland, OR (US);

Charles Kuo, Hillsboro, OR (US);

James Tschanz, Portland, OR (US);

Fatih Hamzaoglu, Portland, OR (US);

Yih Wang, Portland, OR (US);

Roksana Golizadeh Mojarad, San Jose, CA (US);

Inventors:

Arijit Raychowdhury, Duluth, GA (US);

David Kencke, Beaverton, OR (US);

Brian Doyle, Portland, OR (US);

Charles Kuo, Hillsboro, OR (US);

James Tschanz, Portland, OR (US);

Fatih Hamzaoglu, Portland, OR (US);

Yih Wang, Portland, OR (US);

Roksana Golizadeh Mojarad, San Jose, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01); G11C 11/16 (2006.01); G11C 5/12 (2006.01); G11C 13/00 (2006.01);
U.S. Cl.
CPC ...
G11C 11/165 (2013.01); G11C 5/12 (2013.01); G11C 11/1673 (2013.01); G11C 11/1693 (2013.01); G11C 2013/0052 (2013.01); G11C 2013/0071 (2013.01);
Abstract

Methods and systems to read a logic value stored in a magnetic tunnel junction (MTJ)-based memory cell based on a pulsed read current, with time between pulses to permit the MTJ to relax towards the magnetization orientation between the pulses, which may reduce build-up of momentum within the MTJ, and which may reduce and/or eliminate inadvertent re-alignment of a magnetization orientation. A sequence of symmetric and/or non-symmetric pulses may be applied to a wordline (WL) to cause a pre-charged bit line (BL) capacitance to discharge a pulsed read current through the MTJ, resulting in a corresponding sequence of voltage changes on the BL. The BL voltage changes may be integrated over the sequence of read current pulses, and a stored logic value may be determined based on the integrated voltage changes. The pre-charged BL capacitance may also serve as the voltage integrator.


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