The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 20, 2016

Filed:

Dec. 19, 2013
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Shich-Chang Suen, Hsinchu, TW;

Chi-Jen Liu, Taipei, TW;

Ying-Liang Chuang, Zhubei, TW;

Li-Chieh Wu, Hsinchu, TW;

Liang-Guang Chen, Hsinchu, TW;

Ming-Liang Yen, New Taipei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/02 (2006.01); H01L 21/321 (2006.01); H01L 29/66 (2006.01); H01L 21/67 (2006.01);
U.S. Cl.
CPC ...
H01L 21/3212 (2013.01); H01L 21/02074 (2013.01); H01L 29/66545 (2013.01); H01L 21/67051 (2013.01);
Abstract

The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a semiconductor structure including a metal gate (MG) layer formed to fill in a trench between two adjacent interlayer dielectric (ILD) regions; performing a chemical mechanical polishing (CMP) process using a CMP system to planarize the MG layer and the ILD regions; and cleaning the planarized MG layer using a O/DIW solution including ozone gas (O) dissolved in deionized water (DIW). The MG layer is formed on the ILD regions.


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