The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 20, 2016

Filed:

Aug. 21, 2014
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Ru-Gun Liu, Hsinchu County, TW;

Shou-Yen Chou, Hualien County, TW;

Hoi-Tou Ng, Hsinchu, TW;

Ken-Hsien Hsieh, Taipei, TW;

Yi-Yin Chen, Taipei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); G03F 1/36 (2012.01); G03F 7/20 (2006.01); G03F 1/00 (2012.01);
U.S. Cl.
CPC ...
G03F 1/36 (2013.01); G06F 17/5068 (2013.01); G03F 1/14 (2013.01); G03F 1/144 (2013.01); G03F 7/701 (2013.01); G03F 7/70433 (2013.01); G03F 7/70441 (2013.01);
Abstract

A method for making a mask includes receiving an integrated circuit (IC) design layout and identifying at least one targeted-feature-surrounding-location (TFSL) in the IC design layout, wherein TFSL is identified by a model-based approach. The method further includes inserting at least one phase bar (PB) in the IC design layout and performing an optical proximity correction (OPC) to the IC design layout having the at least one PB to form a modified IC design layout. A mask is then fabricated based on the modified IC design layout.


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