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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9443925 B1

PDFFull Text
Date of Patent:
Sep. 13, 2016

Filed:

Sep. 11, 2015

Semiconductor structure with dielectric-sealed doped region

Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Huan-Tsung Huang, Hsin-Chu, TW;

Kuo-Cheng Wu, Hsin-Chu, TW;

Carlos H. Diaz, Mountain View, CA (US);

Assignee:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Attorney:

Slater Matsil, LLP

Primary Examiner:

David Vu

Assistant Examiner:

Jonathan Han

Int. Cl.
CPC ...
H01L 29/51 (2006.01); H01L 29/06 (2006.01); H01L 29/66 (2006.01); H01L 29/08 (2006.01); H01L 29/417 (2006.01); H01L 29/45 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 29/0607 (2013.01); H01L 29/0653 (2013.01); H01L 29/0847 (2013.01); H01L 29/41775 (2013.01); H01L 29/456 (2013.01); H01L 29/66636 (2013.01); H01L 29/66651 (2013.01); H01L 29/78 (2013.01);
Abstract

Leakage current can be substantially reduced by the formation of a seal dielectric in place of the conventional junction between source/drain region(s) and the substrate material. Trenches are formed in the substrate and lined with a seal dielectric prior to filling the trenches with semiconductor material. Preferably, the trenches are overfilled and a CMP process planarizes the overfill material. An epitaxial layer can be grown atop the trenches after planarization, if desired.

Find Patent Forward Citations

Huang, Huan-Tsung. (2016). Semiconductor structure with dielectric-sealed doped region (U.S. Patent No. 9443925). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9443925

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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