The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9433105 B1

PDF
Full Text
Expired
Date of Patent:
Aug. 30, 2016

Filed:

Aug. 25, 2009
Applicants:

Richard Stephen Graf, Gray, ME (US);

Thomas Edward Lombardi, Poughkeepsie, NY (US);

Sudipta Kumar Ray, Wappingers Fall, NY (US);

David Justin West, Essex Junction, VT (US);

Inventors:

Richard Stephen Graf, Gray, ME (US);

Thomas Edward Lombardi, Poughkeepsie, NY (US);

Sudipta Kumar Ray, Wappingers Fall, NY (US);

David Justin West, Essex Junction, VT (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H05K 3/42 (2006.01); H05K 3/40 (2006.01); H05K 3/00 (2006.01);
U.S. Cl.
CPC ...
H05K 3/403 (2013.01); H05K 3/0052 (2013.01); H05K 3/42 (2013.01); H05K 2201/10159 (2013.01); Y10T 29/49165 (2015.01);
Abstract

An electrically insulating substrate is provided. The electrically insulating substrate includes a set of areas to be formed into a set of printed circuit boards. Each of the set of areas is separated from others of the set of areas by a dicing channel. A set of signal wiring conductors is fabricated onto the set of areas of the electrically insulating substrate so that at least one of the set of signal wiring conductors terminates proximate to the dicing channel. A set of plated through holes is fabricated through at least one of the set of areas such that at least one of the set of plated through holes connects to at least one of the set of signal wiring conductors. The electrically insulating substrate is singulated along a set of singulation lines to form the set of printed circuit boards. The singulation lines intersect with the plated through holes, so that a portion of the plated through holes is exposed along the peripheral edge of the resulting printed circuit boards.


Find Patent Forward Citations

Graf, Richard. (2016). Method of fabricating printed circuit boards (U.S. Patent No. 9433105). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9433105

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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