The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 23, 2016
Filed:
Mar. 14, 2013
Maxim Integrated Products, Inc., San Jose, CA (US);
Reynante Alvarado, San Diego, CA (US);
Yi-Sheng A. Sun, San Jose, CA (US);
Arkadii V. Samoilov, Saratoga, CA (US);
Yong L. Xu, Plano, TX (US);
Maxim Integrated Products, Inc., San Jose, CA (US);
Abstract
Wafer-level package (semiconductor) devices are described that have a reinforcement layer formed on an adhesion layer and/or a semiconductor substrate and covering at least a portion of at least one solder bump. Additionally, the reinforcement layer may cover at least a portion of a semiconductor device (e.g., a die) mounted on the semiconductor substrate. In an implementation, the wafer-level package (semiconductor) device may include an integrated circuit chip with an attached die, where the integrated circuit chip has at least one solder bump formed thereon with a reinforcement layer formed on a surface of the integrated circuit chip, where the reinforcement layer embeds the die and covers a portion of the at least one solder bump.