Method for fabricating multiple layers of ultra narrow silicon wires

Abstract

A method for fabricating multiple layers of ultra narrow silicon wires comprises the steps of fabricating wet-etch masking layers of silicon; forming a Fin and source/drain regions located at both ends thereof by epitaxy; forming the multiple layers of ultra narrow silicon wires. The present invention has advantages in that: the atom layer depositing may define the position of the ultra narrow silicon wires accurately, having a good controllability; the anisotropic wet-etch for silicon is performed in a self-stop manner and has a large process window, so that the cross-section shape of the nanowires formed by wet-etch is uniform and smooth. The method to form multiple layers of wet-etch masks at the sidewalls of Fins, in which wet-etch masking layers are formed prior to the epitaxy of Fins is a simple process, so that the multiple sidewall wet-etch masking layers may be obtained by only one etching to the epitaxy window, regardless of the numbers of the wet-etch masking layers; a wire with a diameter less than 10 nm may be fabricated by virtue of the oxidation technology, and thus satisfies the small size devices; the TMAH solution, which is simple and safe to control, is used in the wet-etch for polysilicon, and metal ions are not introduced and thus suitable for the integrated circuit manufacturing process; the method according to the present invention is fully compatible with the planar transistor based on the bulk silicon, and thus the process cost is small.