The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 16, 2016

Filed:

Jan. 16, 2015
Applicants:

Imec Vzw, Leuven, BE;

Taiwan Semiconductor Manufacturing Company, Ltd., HsinChu, TW;

Inventors:

Amey Mahadev Walke, Mumbai, IN;

Anne VanDooren, Mazy, BE;

Krishna Kumar Bhuwalka, HsinChu, TW;

Assignees:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/10 (2006.01); H01L 29/08 (2006.01); H01L 21/306 (2006.01); H01L 21/311 (2006.01); H01L 21/28 (2006.01); H01L 29/739 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66977 (2013.01); H01L 21/28017 (2013.01); H01L 21/30604 (2013.01); H01L 21/31111 (2013.01); H01L 21/31144 (2013.01); H01L 29/0847 (2013.01); H01L 29/1037 (2013.01); H01L 29/66356 (2013.01); H01L 29/66477 (2013.01); H01L 29/7391 (2013.01); H01L 29/78 (2013.01);
Abstract

A tunnel field-effect transistor (TFET) device is provided comprising a semiconductor substrate and a fin structure disposed thereon. The fin structure comprises a channel region and a source region disposed on the channel region. The TFET further comprises a drain region contacting the channel region, wherein the source region and the drain region are of opposite conductivity type. The TFET also comprises a pocket layer covering a gate interface portion of the source region and contacting at least part of the channel region. The TFET further comprises a gate dielectric layer covering the pocket layer and a gate electrode covering the gate dielectric layer. The gate interface portion of the source region comprises at least three mutually non-coplanar surface segments. A method for manufacturing such a TFET device is also provided.


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