The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 02, 2016

Filed:

Mar. 23, 2015
Applicant:

Globalfoundries Singapore Pte. Ltd., Singapore, SG;

Inventors:

Jianbo Yang, Singapore, SG;

Yi Tat Lim, Singapore, SG;

Sung Mun Jung, Singapore, SG;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/115 (2006.01); H01L 29/788 (2006.01); H01L 29/66 (2006.01); H01L 29/423 (2006.01); H01L 21/28 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11524 (2013.01); H01L 21/28273 (2013.01); H01L 29/42328 (2013.01); H01L 29/66553 (2013.01); H01L 29/66825 (2013.01); H01L 29/788 (2013.01);
Abstract

Device and method for forming a device are presented. The method includes providing a substrate prepared with at least a memory cell region having first and second sub-regions and a logic region having input/output (I/O) region and core region. First voltage memory cell is formed in the first sub-region and second voltage memory cell is formed in the second sub-region of the memory cell region of the same substrate. The first voltage memory cell operates in a first voltage and the second voltage memory cell operates in a second voltage which is higher than the first voltage. Each of the first and second voltage memory cells includes a split gate having first and second gates. The first gate is a storage gate having a control gate over a floating gate and the second gate is a wordline. Logic I/O device is formed in the I/O region and logic core device is formed in the core region.


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