The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 02, 2016

Filed:

May. 26, 2015
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Matthew S. Angyal, Stormville, NY (US);

Junjing Bao, Cedar Grove, NJ (US);

Griselda Bonilla, Fishkill, NY (US);

Samuel S. Choi, Beacon, NY (US);

James A. Culp, Newburgh, NY (US);

Thomas W. Dyer, Pleasant Valley, NY (US);

Ronald G. Filippi, Wappingers Falls, NY (US);

Stephen E. Greco, Lagrangeville, NY (US);

Naftali E. Lustig, Croton On Hudson, NY (US);

Andrew H. Simon, Fishkill, NY (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 21/4763 (2006.01); H01L 21/768 (2006.01); H01L 23/532 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76895 (2013.01); H01L 21/7685 (2013.01); H01L 21/76832 (2013.01); H01L 21/76834 (2013.01); H01L 21/76849 (2013.01); H01L 23/53228 (2013.01); H01L 23/53238 (2013.01); H01L 23/53266 (2013.01); H01L 2924/0002 (2013.01);
Abstract

A method of forming a wiring structure for an integrated circuit device includes forming one or more copper lines within an interlevel dielectric layer (ILD); masking selected regions of the one or more copper lines; selectively plating metal cap regions over exposed regions of the one or more copper lines; and forming a conformal insulator layer over the metal cap regions and uncapped regions of the one or more copper lines.


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