The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 26, 2016
Filed:
May. 02, 2014
Sanken Electric Co., Ltd., Niiza-shi, Saitama, JP;
Shin-etsu Handotai Co., Ltd., Tokyo, JP;
Hiroshi Shikauchi, Niiza, JP;
Ken Sato, Miyoshi-machi, JP;
Hirokazu Goto, Minato-ku, JP;
Masaru Shinomiya, Annaka, JP;
Keitaro Tsuchiya, Takasaki, JP;
Kazunori Hagimoto, Takasaki, JP;
SHANKEN ELECTRIC CO., LTD., Saitama, JP;
SHIN-ETSU HANDOTAI CO., LTD., Tokyo, JP;
Abstract
Semiconductor device including: silicon-based substrate; first buffer layer on silicon-based substrate and is formed of first layer containing Al composition and second layer containing less Al than the first layer, the first and second layers being alternately stacked; second buffer layer on the first buffer layer and is formed of third layer containing Al composition and fourth layer containing less Al than the third layer, the third and fourth layers being alternately stacked; and third buffer layer on the second buffer layer and is formed of fifth layer containing Al composition and sixth layer containing less Al than the fifth layer, the fifth and sixth layers being alternately stacked, wherein the second buffer layer contains more Al than the first and third buffer layers. Thus, the semiconductor device leakage can be suppressed while reducing stress which is applied to buffer layer and can improve flatness of active layer upper face.