The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 19, 2016
Filed:
Dec. 28, 2012
Hisashi Yoshida, Kanagawa-ken, JP;
Toshiki Hikosaka, Kanagawa-ken, JP;
Yoshiyuki Harada, Tokyo, JP;
Naoharu Sugiyama, Kanagawa-ken, JP;
Shinya Nunoue, Chiba-ken, JP;
Hisashi Yoshida, Kanagawa-ken, JP;
Toshiki Hikosaka, Kanagawa-ken, JP;
Yoshiyuki Harada, Tokyo, JP;
Naoharu Sugiyama, Kanagawa-ken, JP;
Shinya Nunoue, Chiba-ken, JP;
Kabushiki Kaisha Toshiba, Tokyo, JP;
Abstract
A nitride semiconductor wafer includes a silicon substrate, a stacked multilayer unit, a silicon-containing unit, and an upper layer unit. The silicon substrate has a major surface. The stacked multilayer unit is provided on the major surface. The stacked multilayer unit includes N number of buffer layers. The buffer layers include an i-th buffer layer, and an (i+1)-th buffer layer provided on the i-th buffer layer. The i-th buffer layer has an i-th lattice length Wi in a first direction parallel to the major surface. The (i+1)-th buffer layer has an (i+1)-th lattice length W(i+1) in the first direction. A relation that (W(i+1)−Wi)/Wi≦0.008 is satisfied for all the buffer layers. The silicon-containing unit is provided on the stacked multilayer unit. The upper layer unit is provided on the silicon-containing unit.