The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 19, 2016

Filed:

Sep. 24, 2014
Applicant:

Maxim Integrated Products, Inc., San Jose, CA (US);

Inventors:

Xiansong Chen, Allen, TX (US);

Yi-Sheng A. Sun, San Jose, CA (US);

Kumar Nagarajan, Cupertino, CA (US);

Satbir Madra, Santa Clara, CA (US);

Yong L. Xu, Plano, TX (US);

Assignee:

Maxim Integrated Products, Inc., San Jose, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 23/495 (2006.01); H01L 23/31 (2006.01); H01L 23/29 (2006.01); H01L 21/56 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49503 (2013.01); H01L 21/56 (2013.01); H01L 23/293 (2013.01); H01L 23/3107 (2013.01); H01L 23/49568 (2013.01);
Abstract

A semiconductor package device, electronic device, and fabrication methods are described that include at least one sacrificial contact pad as a portion of the semiconductor package device for preventing and reducing stress on the semiconductor package device and increasing board level reliability. In implementations, the semiconductor package device includes a lead frame substrate including at least one lead frame contact pad and at least one sacrificial contact pad, an integrated circuit device electrically coupled to the lead frame substrate, and an encapsulation layer that encapsulates the lead frame substrate and the integrated circuit device. In implementations, one process for fabricating the semiconductor package device includes placing an integrated circuit device on a lead frame substrate, where the lead frame substrate includes at least one lead frame contact pad and at least one sacrificial contact pad, and encapsulating the integrated circuit device and the lead frame substrate with an encapsulation layer.


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