The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 05, 2016
Filed:
Dec. 20, 2012
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Chung-Cheng Wu, Ju-Bei, TW;
Ali Keshavarzi, Los Altos Hills, CA (US);
Ka Hing Fung, Hsinchu, TW;
Ta-Pen Guo, Cupertino, CA (US);
Jiann-Tyng Tzeng, Hsinchu, TW;
Yen-Ming Chen, Chu-Pei, TW;
Shyue-Shyh Lin, Hsinchu, TW;
Shyh-Wei Wang, Hsinchu, TW;
Sheng-Jier Yang, Zhubei, TW;
Hsiang-Jen Tseng, Hsinchu, TW;
David B. Scott, Plano, TX (US);
Min Cao, Hsinchu, TW;
Abstract
A method of forming an integrated circuit including forming a first diffusion area and a second diffusion area on a substrate, wherein the first diffusion area is configured for a first type transistor, the second diffusion area is configured for a second type transistor. The method further includes forming first source and drain regions in the first diffusion area. The method further includes forming second source and drain regions in the second diffusion area. The method further includes forming a gate electrode extending across the first diffusion area and the second diffusion area. The method further includes forming a first metallic layer, a second metallic layer, and a third metallic layer. The first metallic layer is electrically coupled with the first source region. The second metallic layer is electrically coupled with the first and second drain regions. The third metallic layer is electrically coupled with the second source region.