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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9385059 B1

PDFFull Text
Date of Patent:
Jul. 05, 2016

Filed:

Aug. 28, 2013

Overmolded substrate-chip arrangement with heat sink

Applicant:

Infineon Technologies Ag, Neubiberg, DE;

Inventors:

Peter Ossimitz, Munich, DE;

Juergen Schaefer, Oberhaching, DE;

Liu Chen, Munich, DE;

Markus Dinkel, Unterhaching, DE;

Stefan Macheiner, Kissing, DE;

Assignee:

Infineon Technologies AG, Neubiberg, DE;

Attorney:
Primary Examiner:

Anthony Haughton

Assistant Examiner:

Yahya Ahmad

Int. Cl.
CPC ...
H05K 7/20 (2006.01); H01L 23/34 (2006.01); H01L 21/48 (2006.01); H05K 3/32 (2006.01); H01L 23/367 (2006.01); H01L 23/40 (2006.01); H05K 3/28 (2006.01); H05K 5/00 (2006.01); H01L 23/31 (2006.01); H01L 23/427 (2006.01); H01L 23/498 (2006.01); H05K 1/02 (2006.01);
U.S. Cl.
CPC ...
H01L 23/34 (2013.01); H01L 21/4882 (2013.01); H01L 23/367 (2013.01); H01L 23/4006 (2013.01); H01L 23/4093 (2013.01); H05K 3/284 (2013.01); H05K 3/32 (2013.01); H05K 5/0034 (2013.01); H01L 23/3128 (2013.01); H01L 23/3675 (2013.01); H01L 23/427 (2013.01); H01L 23/49822 (2013.01); H01L 2023/405 (2013.01); H01L 2224/16225 (2013.01); H01L 2924/0002 (2013.01); H01L 2924/13055 (2013.01); H05K 1/0206 (2013.01); H05K 1/0209 (2013.01); H05K 2201/10166 (2013.01); Y10T 29/49146 (2015.01);
Abstract

An electronic device comprises a substrate, at least one electronic chip mounted on and electrically connected to the substrate and being configured as a system control unit for controlling a connected system, a heat removal structure thermally connected to the at least one electronic chip and configured for removing heat generated by the at least one electronic chip upon operation of the electronic device, and an overmolding structure configured for at least partially encapsulating at least the at least one electronic chip and the substrate.

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