The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 28, 2016

Filed:

Jul. 06, 2015
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Inventors:

Joung-Wei Liou, Zhudong Township, TW;

Han-Ti Hsiaw, Zhubei, TW;

Keng-Chu Lin, Ping-Tung, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 23/52 (2006.01); H01L 29/40 (2006.01); H01L 23/532 (2006.01); H01L 21/768 (2006.01); H01L 23/538 (2006.01); H01L 21/48 (2006.01); H01L 23/522 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5329 (2013.01); H01L 21/486 (2013.01); H01L 21/76825 (2013.01); H01L 21/76826 (2013.01); H01L 21/76829 (2013.01); H01L 23/5226 (2013.01); H01L 23/5384 (2013.01); H01L 23/53228 (2013.01); H01L 23/53295 (2013.01); H01L 2924/0002 (2013.01);
Abstract

Some embodiments of the present disclosure relate to an integrated circuit device. The integrated circuit device includes a semiconductor substrate, and an inter-level dielectric layer arranged over the semiconductor substrate. An etch-stop layer is arranged over the inter-level dielectric layer. The etch-stop layer comprises silicon oxide, silicon nitride, or silicon oxynitride, and has a density greater than or equal to 2.15 g/cm.


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