The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 21, 2016

Filed:

Sep. 12, 2014
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Chin-Chi Wang, New Taipei, TW;

Chien-Chih Lee, New Taipei, TW;

Tien-Wei Chiang, Taipei, TW;

Ching-Wei Tsai, Hsinchu, TW;

Chih-Ching Wang, Jinhu Township, TW;

Jon-Hsu Ho, New Taipei, TW;

Wen-Hsing Hsieh, Hsinchu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 21/336 (2006.01); H01L 27/088 (2006.01); H01L 29/78 (2006.01); H01L 29/45 (2006.01); H01L 29/06 (2006.01); H01L 23/528 (2006.01); H01L 21/283 (2006.01); H01L 21/306 (2006.01); H01L 21/768 (2006.01); H01L 21/31 (2006.01);
U.S. Cl.
CPC ...
H01L 27/088 (2013.01); H01L 21/283 (2013.01); H01L 21/30604 (2013.01); H01L 21/31 (2013.01); H01L 21/76897 (2013.01); H01L 23/528 (2013.01); H01L 29/0649 (2013.01); H01L 29/45 (2013.01); H01L 29/66666 (2013.01); H01L 29/7827 (2013.01);
Abstract

A series-connected transistor structure includes a first source, a first channel-drain structure, a second channel-drain structure, a gate dielectric layer, a gate, a first drain pad and a second drain pad. The first source is over a substrate. The first channel-drain structure is over the first source and includes a first channel and a first drain thereover. The second channel-drain structure is over the first source and substantially parallel to the first channel-drain structure and includes a second channel and a second drain thereover. The gate dielectric layer surrounds the first channel and the second channel. The gate surrounds the gate dielectric layer. The first drain pad is over and in contact with the first drain. The second drain pad is over and in contact with the second drain, in which the first drain pad and the second drain pad are separated from each other.


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