Forming interconnect features with reduced sidewall tapering

Abstract

A method includes forming a stack of materials including a first dielectric layer having a conductive feature positioned therein, and a second dielectric layer positioned above the first dielectric layer. An etch mask including a plurality of spaced apart mask elements is formed above the second dielectric layer. The mask elements define at least a first via opening exposing the second dielectric layer. A patterning layer is formed above the etch mask. A second via opening is formed in the patterning layer to expose the first via opening in the etch mask. The second dielectric layer is etched through the second via opening to define a third via opening in the second dielectric layer exposing the conductive feature. The patterning layer and the etch mask are removed. A conductive via contacting the conductive feature is formed in the third via opening.