The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 14, 2016

Filed:

Jun. 28, 2013
Applicant:

Stats Chippac, Ltd., Singapore, SG;

Inventors:

Byung Tai Do, Singapore, SG;

Arnel Trasporto, Singapore, SG;

Linda Pei Ee Chua, Singapore, SG;

Asri Yusof, Singapore, SG;

Assignee:

STATS ChipPAC Pte. Ltd., Singapore, SG;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/52 (2006.01); H01L 21/50 (2006.01); H01L 23/31 (2006.01); H01L 23/495 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/3121 (2013.01); H01L 21/4832 (2013.01); H01L 21/568 (2013.01); H01L 23/49582 (2013.01); H01L 24/97 (2013.01); H01L 24/06 (2013.01); H01L 24/32 (2013.01); H01L 24/48 (2013.01); H01L 24/49 (2013.01); H01L 24/83 (2013.01); H01L 24/85 (2013.01); H01L 24/92 (2013.01); H01L 2224/04042 (2013.01); H01L 2224/06135 (2013.01); H01L 2224/32245 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48247 (2013.01); H01L 2224/49433 (2013.01); H01L 2224/83191 (2013.01); H01L 2224/8592 (2013.01); H01L 2224/85411 (2013.01); H01L 2224/85424 (2013.01); H01L 2224/85439 (2013.01); H01L 2224/85444 (2013.01); H01L 2224/85447 (2013.01); H01L 2224/85455 (2013.01); H01L 2224/92247 (2013.01); H01L 2224/94 (2013.01); H01L 2224/97 (2013.01); H01L 2924/01322 (2013.01); H01L 2924/12041 (2013.01); H01L 2924/12042 (2013.01); H01L 2924/12043 (2013.01); H01L 2924/13091 (2013.01); H01L 2924/15153 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/181 (2013.01); H01L 2924/1815 (2013.01);
Abstract

A semiconductor device has a substrate including a base and a plurality of conductive posts extending from the base. A semiconductor die is disposed on a surface of the base between the conductive posts. An interconnect structure is formed over the semiconductor die and conductive posts. An adhesive layer is disposed over the semiconductor die. A conductive layer is disposed over the adhesive layer. An encapsulant is deposited over the semiconductor die and around the conductive posts. One or more conductive posts are electrically isolated from the substrate. The conductive layer is a removable or sacrificial cap layer. The substrate includes a wafer-shape, panel, or singulated form. The semiconductor die is disposed below a height of the conductive posts. An interconnect structure is formed over the semiconductor die, encapsulant, and conductive posts.


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