The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 14, 2016
Filed:
Sep. 29, 2014
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Weng Hong Teh, Phoenix, AZ (US);
Vinodhkumar Raghunathan, Chandler, AZ (US);
Assignee:
INTEL CORPORATION, Santa Clara, CA (US);
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/31 (2006.01); H01L 21/768 (2006.01); H01L 23/00 (2006.01); H01L 21/56 (2006.01); H01L 25/065 (2006.01); H01L 23/538 (2006.01); H01L 25/10 (2006.01); H01L 21/48 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76879 (2013.01); H01L 21/568 (2013.01); H01L 23/3121 (2013.01); H01L 23/3192 (2013.01); H01L 23/5383 (2013.01); H01L 23/5389 (2013.01); H01L 24/14 (2013.01); H01L 24/19 (2013.01); H01L 24/25 (2013.01); H01L 24/82 (2013.01); H01L 25/0657 (2013.01); H01L 21/4857 (2013.01); H01L 24/13 (2013.01); H01L 24/16 (2013.01); H01L 24/73 (2013.01); H01L 25/105 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/04105 (2013.01); H01L 2224/12105 (2013.01); H01L 2224/131 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/2501 (2013.01); H01L 2224/73259 (2013.01); H01L 2224/821 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/1035 (2013.01); H01L 2225/1058 (2013.01); H01L 2924/12042 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1434 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/18162 (2013.01);
Abstract
Electronic assemblies including substrates and their manufacture are described. One assembly includes a die embedded in a dielectric layer in a multilayer substrate, and a dielectric region embedded in the dielectric layer in the multilayer substrate. The multilayer substrate includes a die side and a land side, with the first dielectric region and the dielectric layer extending to the die side. A plurality of vias are positioned within the first dielectric region, the vias extending to pads on the die side. Other embodiments are described and claimed.