The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 07, 2016
Filed:
May. 19, 2015
Globalfoundries Inc., Grand Cayman, KY;
Laegu Kang, Hopewell Junction, NY (US);
Vara Govindeswara Reddy Vakada, Fishkill, NY (US);
Michael Ganz, Fishkill, NY (US);
Yi Qi, Fishkill, NY (US);
Puneet Khanna, Wappingers Falls, NY (US);
Sri Charan Vemula, Fishkill, NY (US);
Srikanth Samavedam, Fishkill, NY (US);
GLOBALFOUNDRIES INC., Grand Cayman, KY;
Abstract
A method of forming SSRW FETs with controlled step height between a field oxide and epitaxially grown silicon and the resulting devices are provided. Embodiments include providing a SiN layer on a substrate, forming first, second, and third spaced STI regions of field oxide through the SiN layer and into the substrate, removing a top portion of the field oxide for each STI region by a controlled deglaze, removing the SiN layer, forming an n-type region in the substrate between the first and second STI regions and a p-type region in the substrate between the second and third STI regions, and epitaxially growing a Si based layer on the substrate over the n-type and p-type regions.