The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 07, 2016
Filed:
Dec. 22, 2014
Renesas Electronics Corporation, Kawasaki-shi, Kanagawa, JP;
Takahiko Kato, Hitachinaka, JP;
Hiroshi Nakano, Tokai, JP;
Haruo Akahoshi, Hitachi, JP;
Yuuji Takada, Kawasaki, JP;
Yoshimi Sudo, Akiruno, JP;
Tetsuo Fujiwara, Hitachinaka, JP;
Itaru Kanno, Takarazuka, JP;
Tomoryo Shono, Kawanishi, JP;
Yukinori Hirose, Suita, JP;
RENESAS ELECTRONICS CORPORATION, Tokyo, JP;
Abstract
A semiconductor device having Cu wiring including a basic crystal structure which can reduce surface voids, and an inspecting technique for the semiconductor device. In the semiconductor device, surface voids can be reduced down to 1/10 or less of a current practical level by specifying a barrier layer and a seed layer and setting a proportion (frequency) of occupation of a coincidence site lattice (CSL) boundary having a grain boundary Sigma value 27 or less to all crystal grain boundaries of a Cu wiring to 60% or higher. Alternatively, a similar effect of surface void reduction can be obtained by specifying a barrier layer and a seed layer and setting a proportion (frequency) of occupation of a coincidence site lattice (CSL) boundary having a grain boundary Sigma value 3 to all crystal grain boundaries of a Cu wiring to 40% or higher.