The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 07, 2016
Filed:
Oct. 18, 2011
Lei Shi, Jiangsu, CN;
Yujuan Tao, Jiangsu, CN;
Guohua Gao, Jiangsu, CN;
Naomi Masuda, Jiangsu, CN;
Koichi Meguro, Jiangsu, CN;
Lei Shi, Jiangsu, CN;
Yujuan Tao, Jiangsu, CN;
Guohua Gao, Jiangsu, CN;
Naomi Masuda, Jiangsu, CN;
Koichi Meguro, Jiangsu, CN;
Nantong Fujitsu Microelectronics Co., Ltd., Nantong, Jiangsu, CN;
Abstract
Provided is a method for chip packaging, including the steps of: providing a semi-packaged wafer which has a cutting trail and a metal bonding pad of the chip; forming on the metal bonding pad a sub-ball metal electrode, using a selective formation process; forming a protective layer on the wafer in a region not including the sub-ball metal electrode, with the protective layer covering the cutting trail; forming a solder ball on the sub-ball metal electrode; dicing the wafer along the cutting trail. The present invention can prevent metal in the cutting trail from being affected during the production of the sub-ball metal electrode, and protect the lateral sides of a discrete chip after cutting. The process flow thereof is simple, and enhances the efficiency of the packaging as well as its yield.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile