The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 31, 2016

Filed:

Aug. 04, 2014
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Lee Choon Kuan, Singapore, SG;

David J. Corisis, Nampa, ID (US);

Chin Hui Chong, Singapore, SG;

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/495 (2006.01); H01L 23/498 (2006.01); H01L 25/065 (2006.01); H01L 25/16 (2006.01); H01L 25/00 (2006.01); H01L 21/66 (2006.01);
U.S. Cl.
CPC ...
H01L 24/92 (2013.01); H01L 22/14 (2013.01); H01L 23/3121 (2013.01); H01L 23/49531 (2013.01); H01L 23/49861 (2013.01); H01L 24/96 (2013.01); H01L 24/97 (2013.01); H01L 25/0657 (2013.01); H01L 25/16 (2013.01); H01L 25/50 (2013.01); H01L 22/32 (2013.01); H01L 24/48 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/73265 (2013.01); H01L 2224/92127 (2013.01); H01L 2224/97 (2013.01); H01L 2225/0651 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06527 (2013.01); H01L 2924/01079 (2013.01); H01L 2924/01087 (2013.01); H01L 2924/19041 (2013.01);
Abstract

A semiconductor device package includes a land grid array package. At least one semiconductor die is mounted to an interposer substrate, with bond pads of the semiconductor die connected to terminal pads on the same side of the interposer substrate as the at least one semiconductor die. Terminal pads of the interposer substrate may be electrically connected to either or both of a peripheral array pattern of lands and to a central, two-dimensional array pattern of pads, both array patterns located on the opposing side of the interposer substrate from the at least one semiconductor die. Additional components, active, passive or both, may be connected to pads of the two-dimensional array to provide a system-in-a-package. Lead fingers of a lead frame may be superimposed on the opposing side of the interposer substrate, bonded directly to the land grid array land and wire bonded to pads as desired for repair or to ease routing problems on the interposer. The land grid array package may be mounted to a carrier substrate, and the lands wire bonded to conductive pads on the carrier substrate. Methods of fabrication are also disclosed.


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