The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 31, 2016
Filed:
Jan. 05, 2015
Wei-sheng Lei, San Jose, CA (US);
Jungrae Park, Santa Clara, CA (US);
Prabhat Kumar, Fremont, CA (US);
James S. Papanu, San Rafael, CA (US);
Brad Eaton, Menlo Park, CA (US);
Ajay Kumar, Cupertino, CA (US);
Wei-Sheng Lei, San Jose, CA (US);
Jungrae Park, Santa Clara, CA (US);
Prabhat Kumar, Fremont, CA (US);
James S. Papanu, San Rafael, CA (US);
Brad Eaton, Menlo Park, CA (US);
Ajay Kumar, Cupertino, CA (US);
Applied Materials, Inc., Santa Clara, CA (US);
Abstract
Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a mask above the semiconductor wafer, the mask composed of a layer covering and protecting the integrated circuits. The mask is then patterned with a line shaped laser beam profile laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then plasma etched through the gaps in the patterned mask to singulate the integrated circuits.