The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 17, 2016
Filed:
Feb. 07, 2013
Applicants:
Yu-ru Chang, Hsinchu County, TW;
Yu-fang Hsia, Hsinchu, TW;
Ling-chih Chou, Taipei, TW;
Inventors:
Assignees:
Global Unichip Corp., Hsinchu, TW;
Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu, TW;
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/03 (2006.01); H05K 1/02 (2006.01); H01L 23/498 (2006.01); H01L 23/60 (2006.01);
U.S. Cl.
CPC ...
H05K 1/0286 (2013.01); H01L 23/49822 (2013.01); H01L 23/49838 (2013.01); H01L 23/60 (2013.01); H01L 2924/0002 (2013.01); H05K 2201/09127 (2013.01); H05K 2201/09972 (2013.01); H05K 2203/0228 (2013.01); Y10T 29/49155 (2015.01);
Abstract
The present invention discloses a package substrate layout design to achieve multiple substrate functions for engineering development and verification. The substrate layout contains a connection structure to connect to a plurality of power/ground domains on the package substrate. With different combination of the cutting lines on the package substrate, the invention can achieve multiple substrate functions without impacting the customer's PCB or system board design and provide cost effective and fast cycle time for engineering development phase.