The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 03, 2016

Filed:

Oct. 03, 2014
Applicants:

Zhihong Zhang, Chandler, AZ (US);

Hongning Yang, Chandler, AZ (US);

Jiang-kai Zuo, Chandler, AZ (US);

Inventors:

Zhihong Zhang, Chandler, AZ (US);

Hongning Yang, Chandler, AZ (US);

Jiang-Kai Zuo, Chandler, AZ (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 23/00 (2006.01); H01L 21/78 (2006.01); H01L 23/31 (2006.01); H01L 23/58 (2006.01);
U.S. Cl.
CPC ...
H01L 23/562 (2013.01); H01L 21/78 (2013.01); H01L 23/3171 (2013.01); H01L 23/585 (2013.01); H01L 2924/0002 (2013.01);
Abstract

Die structures for electronic devices and related fabrication methods are provided. An exemplary die structure includes a diced portion of a semiconductor substrate that includes a device region having one or more semiconductor devices fabricated thereon and an edge sealing structure within the semiconductor substrate that circumscribes the device region. In one or more embodiments, the edge sealing structure includes a conductive material that contacts a handle layer of semiconductor material, a crackstop structure is formed overlying the sealing structure, wherein the crackstop structure and the edge sealing structure provide an electrical connection between the handle layer and an active layer of semiconductor material that overlies a buried layer of dielectric material on the handle layer.


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