The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 03, 2016

Filed:

Sep. 18, 2007
Applicants:

Sungmin Song, Inchon, KR;

Seungyun Ahn, Ichon-si, KR;

Johyun Bae, Seoul, KR;

Jong-woo Ha, Seoul, KR;

Inventors:

Sungmin Song, Inchon, KR;

SeungYun Ahn, Ichon-si, KR;

JoHyun Bae, Seoul, KR;

Jong-Woo Ha, Seoul, KR;

Assignee:

STATS ChipPAC Ltd., Singapore, SG;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/56 (2006.01); H01L 23/31 (2006.01); H01L 25/03 (2006.01); H01L 25/065 (2006.01); H01L 25/10 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 21/563 (2013.01); H01L 23/3128 (2013.01); H01L 25/03 (2013.01); H01L 25/0657 (2013.01); H01L 25/105 (2013.01); H01L 24/48 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/06135 (2013.01); H01L 2224/06136 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/4824 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48225 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/73203 (2013.01); H01L 2224/73215 (2013.01); H01L 2224/73253 (2013.01); H01L 2224/73265 (2013.01); H01L 2225/0651 (2013.01); H01L 2225/0652 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06558 (2013.01); H01L 2225/1023 (2013.01); H01L 2225/1058 (2013.01); H01L 2225/1088 (2013.01); H01L 2924/12041 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/1815 (2013.01); H01L 2924/19107 (2013.01); H01L 2924/3511 (2013.01);
Abstract

An integrated circuit package system with multi-chip module is provided including: providing an upper substrate having an upper chip thereon; positioning a lower chip under the upper chip, the lower chip having bottom interconnects thereon; encapsulating the upper chip and the lower chip with a chip encapsulant on the upper substrate with the bottom interconnects exposed; mounting the lower chip over a lower substrate with a gap between the chip encapsulant and the lower substrate; and filling the gap with a package encapsulant or chip attach adhesive.


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