The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 26, 2016

Filed:

May. 28, 2014
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Natalie B. Feilchenfeld, Jericho, VT (US);

BethAnn Lawrence, Essex Junction, VT (US);

Yun Shi, South Burlington, VT (US);

Assignee:

GLOBALFOUNDRIES Inc., Grand Cayman, KY;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/76 (2006.01); H01L 23/48 (2006.01); H01L 21/768 (2006.01); H01L 21/762 (2006.01); H01L 29/06 (2006.01); H01L 27/12 (2006.01);
U.S. Cl.
CPC ...
H01L 23/481 (2013.01); H01L 21/76224 (2013.01); H01L 21/76898 (2013.01); H01L 27/1207 (2013.01); H01L 29/0649 (2013.01);
Abstract

A method of forming a semiconductor structure in a semiconductor-on-insulator (SOI) substrate and semiconductor structure so formed are provided. The SOI substrate includes a semiconductor layer; a bulk semiconductor region underlying the semiconductor layer; and an insulation layer between the two. The method includes substantially simultaneously forming a first opening and a second opening extending from the semiconductor layer to the conductive region; introducing an insulating material to the side walls of the first opening; at least partially filling the first opening with a semiconductor material to provide an ohmic contact trench; and at least partially filling the second opening with an insulating material to form a device isolation trench. Insulating regions, for example, shallow trench isolation (STI) regions, may be formed about the device isolation trench and the ohmic contact trench. Semiconductor structures are also provided. The benefits of combining the features of SOI and STI structures are provided.


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